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uart16550
- uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and ot
This_is_pci-wishbone_nuclear_and_16450_serial_port
- 这是用pci-wishbone核和16450串口核在xilinx的FPGA上实现的。-This is pci-wishbone nuclear and 16450 serial port on the nucleus in xilinx FPGA-implemented.
ata_latest.tar
- The OCIDEC (OpenCores IDE Controller) is a WISHBONE rev.B2 compliant ATA/ATAPI-5 host implementation. The ATA (AT Attachment) interface, also known as IDE (Integrated Drive Electronics) interface, provides a simple i
wishbone_m4_s8
- wishbone 骨幹部份 RTL 源碼, 以verilog 寫成, 自創. 支源 4 master 及 8 slave-wishbone core, write by verilog, support 4 master and 8 slaver. language: verilog.
vga_lcd_latest.tar
- 此VGA/LCD控制器是revB.3版本的基于WISHBONE总线,适用于驱动CRT和LCD显示屏的嵌入式VGA驱动。-VGA/LCD Controller core is a WISHBONE revB.3 compliant embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and
UART_IP_core_for_wishbone
- 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
ahb2wishbone_latest.tar
- AHB总线到wishbone总线的转化的Verilog源码-AHB to wishbone verilog source code
wb_to_amba_latest.tar
- wishbone总线到AMBA总线的转换,做总线的朋友可以-wishbone bus to the AMBA bus conversion, so friends can see the bus
wb_conmax_latest.tar
- WISHBONE总线的接口实现,采用Verilog完成。能同时连接8个主设备和16个从设备。-WISHBONE bus interface, the use of Verilog to complete. Can simultaneously connect up to 8 masters and 16 slaves.
led_driver
- LED display verilog code. to generate clocks and wishbone interface
AHB_to_Wishbone_Verilog
- 该源代码包是AHB总线到Wishbone总线的交接器,包括以下4个部分:RTL源代码,测试平台,软件测试程序,说明文档。-This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help document
wb_conbus
- wishbone的verilog代码的实现,标准的协议规范-wishbone of the verilog code implementation, the standard protocol specification
wbspec_b4
- wishbone总线的规范介绍,很详细,很不错-wishbone bus specification describes, in great detail, very good
wishbone
- wishbone协议,IC设计必备 -wishbone agreement, IC design IC design must have the necessary
wb_flash_latest.tar
- its a flash controller which is compatable with wishbone
Digipot_wb_interface
- Generic Wishbone Slave interface for AD5204 driver. Instantiable in any platform.
i2c_latest[1].tar
- I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications pr
WISHBONE
- WISHBONE片上系统互联总线结构规范-WISHBONE System-on-chip interconnect bus architecture specification
uart_wb
- 兼容wishbone bus的uart模块,方便用户修改,时候初学者学习-Compatible with wishbone bus the uart module, user-friendly changes beginners to learn when
spilicheng
- spi接口的wishbone总线的实现,能够实现spi控制器的基本功能,书上例程-spi interface wishbone bus, to achieve the basic functions of the spi controller to book routine