[VHDL编程] cam_generic_8s

说明：verilog 开发实例 无线通 信网络-verilog examples of the development of wireless communication networks
<鹧鸪天> 在 2025-06-08 上传 | 大小：3kb | 下载：0

[VHDL编程] myfir

说明：VHDL设计的FIR滤波器，有Matlab设计文件，Quartus II工程以及Modelsim仿真结果和说明文件-VHDL design FIR filters, Matlab design documents, Quartus II project and Modelsim simulation results and documentation
<fangying> 在 2025-06-08 上传 | 大小：2.73mb | 下载：0

[VHDL编程] hierarchical-code

说明：Abstract—This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically ad
<shankar.m> 在 2025-06-08 上传 | 大小：2kb | 下载：0

[VHDL编程] handbook

说明：Abstract—This paper presents a Viterbi-based test compression algorithm/architecture that provides high encoding efficiency and scalability with respect to the number of test channels. The proposed scheme finds a set of compressed test vectors
<shankar.m> 在 2025-06-08 上传 | 大小：3.65mb | 下载：0

[VHDL编程] upload

说明：A major obstacle that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with x-values are compacted, some of the outputs of the compactor may als
<shankar.m> 在 2025-06-08 上传 | 大小：33kb | 下载：0

[VHDL编程] source

说明：A major obstacle that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with x-values are compacted, some of the outputs of the compactor may als
<shankar.m> 在 2025-06-08 上传 | 大小：10kb | 下载：0

[VHDL编程] vhtoverilog

说明：A major obstacle of thge code is to convert verilog to convert an vhdl code that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with x-values ar
<shankar.m> 在 2025-06-08 上传 | 大小：27.96mb | 下载：1

[VHDL编程] vhdl-all-english

说明：A major obstacle that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with s and the correctness of the compactor inputs cannot be verified at
<shankar.m> 在 2025-06-08 上传 | 大小：557kb | 下载：0

[VHDL编程] src

说明：VGA条形图案的显示，用verilog写的-this Source code is about the display of Stripe pattern
<胡> 在 2025-06-08 上传 | 大小：5kb | 下载：0

[VHDL编程] src1

说明：关于串口通信的一段源代码， 希望能有帮助-this source code is about Serial communication
<胡> 在 2025-06-08 上传 | 大小：5kb | 下载：0

[VHDL编程] led_flow

说明：verilog 控制灯的闪烁，运用状态机写的-this code is about the Flicker of light
<胡> 在 2025-06-08 上传 | 大小：1kb | 下载：0

[VHDL编程] zifu

说明：关于用vga显示字符的一段程序，verilog-this code is about the display of Character
<胡> 在 2025-06-08 上传 | 大小：3kb | 下载：0