资源列表
[VHDL编程] simple_function
说明:This a rc5 encryption simple function code. Note that keys here are already been selected. You can add a vhdl code for key generation is well.-This is a rc5 encryption simple function code. Note that keys here are already been selected. You can add a<harsh shah> 在 2025-08-07 上传 | 大小:2kb | 下载:0
[VHDL编程] FIFO
说明:用verilog语言编写的FIFO文件,这是一种传统的按序执行方法,先进入的指令先完成并引退,跟着才执行第二条指令,希望能够帮助读者-With verilog language FIFO file, which is a traditional sequential execution method, first enter the command to finish and retire, followed by only the second instruction execution, h<huawei> 在 2025-08-07 上传 | 大小:2kb | 下载:0
[VHDL编程] liushuideng
说明:流水灯,控制方向,对系统时钟进行分频,奇偶数闪亮-Water lights, control direction, the system clock frequency, odd even flashing<陈宇璐> 在 2025-08-07 上传 | 大小:2kb | 下载:0
[VHDL编程] Random-sequence-of-test
说明:随机序列的测试源码,使用verilog编写,感觉很有用,希望大家喜欢-Random sequence of test source, the use verilog to write, feel useful, I hope you like<李丽> 在 2025-08-07 上传 | 大小:2kb | 下载:0
[VHDL编程] 151019_halfadder
说明:此程序是FPGA 中用VHDL语言来实现半加器的功能,对于初学者很有参考价值。-This program is FPGA using VHDL language to achieve a half-adder function, a good reference for beginners.<安安> 在 2025-08-07 上传 | 大小:2kb | 下载:0
[VHDL编程] dfe_filter
说明:DEF算法的FIR滤波器verilog代码,内有乘法器IP核,可直接仿真使用-DEF algorithm for FIR filter verilog code with multiplier IP core, can be directly used simulation<右下角> 在 2025-08-07 上传 | 大小:2kb | 下载:0