搜索资源列表
SOPC-based-boundary-scan-test-controller-IP-core-d
- 基于SOPC的边界扫描测试控制器IP核设计SOPC-based boundary scan test controller IP core design-SOPC-based boundary scan test controller IP core design
Embedesign
- 嵌入式ATA主机控制器IP核设计host controller -Embedded ATA host controller IP core design
How-to-adiet-a-ip-core
- 告诉你如何编写一个IP核，对于FPGA 的学习很有帮助-Tell you how to write a IP core, FPGA' s very helpful for
fft_2011_3_23(COMPLETE-FFT1024)
- VERILOG FFT IP核调用，以及其控制文件-VERILOG FFT IP core call, as well as its control file
FSK
- 利用FPGA内的IP核来实现FSK，Using FPGA to realize the IP core FSK。-Using FPGA to realize the IP core FSK,
SOPC-movie-IP
- 基于SOPC 的视频编解码IP 核的设计-SOPC-based video codec IP core design
sdram_ip_doc_preliminary
- 关于的SDRAM ip核相关资料汇总，SDRAM,SDRAM-On the SDRAM ip summary of nuclear-related materials, SDRAM, SDRAM
SDRAM_ipcore_
- Altera SDRAM ip核详解-Altera SDRAM ip nuclear Detailed
verilog-usb--protel-design
- 基于FPGA的usb2.0 ip核设计，所用的语言是verilog-FPGA-based usb2.0 ip core design, the language used is the verilog
multiplier_ip
- 基于IP核的乘法器设计，multiplier_ip中包含完整的工程设计文件，用户可以在Xilinx ISE下运行-Based on IP core of design, multiplier_ip on time-multiplier contain complete engineering documents, users can run Xilinx ISE
CoreSPI_21_eval
- SPI IP核源码，包括Verilog和VHDL两种语言源码-SPI IP core source code, including the two languages Verilog and VHDL source code
ISE_lab17
- 本实验使用 XILINX 提供的IP 核，并例化该IP 核来实现正弦信号发生器的功能。由于 ISE 中有DDS（Direct Digital Synthesizer 5.0）IP 核，因此只需要编写一个顶层文件来调用 Core Generator 生成的IP 即可。-This study provides the IP core using the XILINX, and cases of the IP core to achi
LCD12864
- 基于 NIOS II的LCD12864 IP核设计，有了这个可以直接使用LCD12864-NIOS II of LCD12864 IP-based core design, with this can be used directly LCD12864
Quartus-IP---usage
- 关于IP核的应用的说明 很好的参考手册 不要错过-IP core applications on the instructions not to miss a good reference manual
mypro_synfifo
- 基于IP核RAM的同步fifo设计，工程使用Xilinx的开发软件ISE-RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE
CPCI_PCIbus
- 为构建一个紧凑、灵活的 CPC I系统,在 IP核的基础上,采用 FPGA来实现 PCI总线接口电路。-To construct a compact and flex ible CPC I syste m, the PCI i nte rface c i rcuit i s i mp l em ented by FPGA based on IP core。
fft_ug
- altera的FFT IP核的用户手册，介绍了如何使用ALTERA IP核生成FFT核，如何设置参数并讲述了如何仿真，适用于通信方面的FPGA设计工程师，学生。-altera' s FFT IP core user manual describes how to use the ALTERA IP core generated FFT core, how to set parameters and describes how to
vga-ip-core
- vga ip core 资料 说明如定制一个ip核-vga ip core information such as a custom ip core
FFT
- verilog 实现FFT IP核的控制，借鉴给需要学习的朋友-verilog achieve FFT IP core control, reference to the need to learn a friend
DDR-SDRAM_IP_core
- DDR-SDRAM接口模块verilog源代码，可用作IP核使用，已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven