搜索资源列表
free_IP_1
- 来自于OpenCores组织的开放IP核，非常专业，大牛编写。-OpenCores organizations from open IP core, very professional, big cattle preparation.
free_IP_2
- 来自于OpenCores组织的开放IP核，非常专业，大牛编写。-OpenCores organizations from open IP core, very professional, big cattle preparation.
FPGA_UARTIP
- 基于FPGA的UARTIP核设计与实现.pdf-FPGA-Based Design and Implementation of UARTIP nuclear. Pdf
IP-DAC
- 描述了一个8位二进制输入的DAC 文章中包含源代码 采用数字化技术、在测控系统中用IP核实现D/A转换，并且在1片可编程逻辑器件中实现。它不受温度的影响，既可保持高分辨率，又可降低对电路精度和稳定度的要求，并减少元件的数量。 -Described an 8-bit binary DAC input article contains the source code using digital technology, i
basicforVHDLIPcoretest
- 基于VHDL语言的IP核验证 -VHDL-based IP core verification language
EHERNETIPcore
- 该文件包含以太网IP核的相关代码，一共包含24个VERILOG源代码-This document contains the relevant Ethernet IP core code, a total of 24 includes Verilog source code
camera.tar
- 摄像头的硬件函数，ip核，用于xilinx公司的virtex4 fpga-Camera
SRAM_16Bit_512K
- Verilog 编写的IP核，512K的16位SRAM-Written in Verilog IP core, 512K 16-bit SRAM
DM9000A
- Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核-Verilog prepared DM9000A the IP core network card, altera company sent DE2 System source of nuclear
ps2_ipcore_design
- 电子测量技术 ELECTR0NIC MEASI瓜EMENT TECHN0L0GY 第29卷第3期 2006年6月 PS／2设备接口IP核设计 王 豪黄启俊常 胜 (武汉大学物理学院微电子与固体电子学实验室武汉430072) 摘要：用Verilog硬件描述语言实现了PS／2设备接口的II)核设计，详细描述了II)核的结构划分和各模块的 设计思想，并在FPGA上进行验证。结果表明此 核功能正确，可以方便地在S
mdct.tar
- 图像编码 如H263 264 AVS等编码都要用DCT变换，DCT变换IP核很有用-Image coding, such as H263 264 AVS must be used, such as DCT transform coding, DCT transform IP core very useful
CF_card_base_on_NiosII
- 基于NIOS的CF卡应用(包括了软件和硬件),ALTERA的IP库中只提供了底层的硬件寄存器描述头文件.这是个基于IP核HAL的软件,以及相应的硬件设计示例.-NIOS based on the CF card applications (including the software and hardware), ALTERA the IP library provides only the bottom of the first do
C8051
- VHDL版的C8051核(C8051).evatronix公司的IP核-VHDL version of the C8051 core (C8051). Evatronix company s IP core
sha1_v01
- SHA-1加密算法的IP核，内涵文档，仿真测试文件-SHA-1 encryption algorithm of the IP core, the connotation of documents, simulation test file
IPOFPIC
- pic单片机的源代码,基于此IP核可以自己修改单片机的外围设备,并在此基础上开发自己的单片机.-SCM pic source code, based on this IP core can modify MCU peripherals, and on this basis to develop their own single-chip microcomputer.
USB
- 用VHDL实现的USB IP核，大家可以参考下-Use VHDL to achieve USB IP core, we can refer to the following
I2C
- 详细描述了I2C的技术规范 版本号为2.1 是采用VHDL编写I2C的IP核的一本不错的参考资料-A detailed descr iption of the I2C specification version 2.1 is the use of VHDL for the preparation of the IP core I2C a good reference
vhdl_source
- MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx-MP3 for XPLA3 XILINX.CPLD, must XILINX use of FPGA chip, as is the Xilinx IP core
AVR_Core.tar
- vhdl语言编写的AVR单片机IP核，里面有testbench和说明文档。-VHDL language AVR Single Chip IP core, there are Testbench and documentation.
can.tar
- can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases