搜索资源列表
发布15个Altera的IP的源码
- ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.-Altera FPGA IP core of the source code for the use of Altera FPGA design to provide the relevant information.
8-bit-mcu-ip-core-design-and-verification
- 万方数据库中载的，关于IP核设计和验证方面的论文-popular database containing, for the IP core design and certification papers
IP-DAC
- 描述了一个8位二进制输入的DAC 文章中包含源代码 采用数字化技术、在测控系统中用IP核实现D/A转换，并且在1片可编程逻辑器件中实现。它不受温度的影响，既可保持高分辨率，又可降低对电路精度和稳定度的要求，并减少元件的数量。
ip
- 15个免费的ip核包含avr core，core arm核
fpga-jianpan-ip-core
- 基于fpga的键盘设计ip核的vhdl源代码-Ip fpga design of the keyboard based on the vhdl source code for nuclear
ethernet10-100M-IP-core
- 以太网10-100M IP核Verilog源码，可综合-Ethernet 10-100M IP core Verilog source code can be integrated
USB-1.1-IP-CORE-VHDL
- USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code
ise-ip-core
- IP核包括硬IP与软IP。调用IP核能避免重复劳动，大大减轻设计人员的工作量。-IP cores, including hard IP and soft IP. IP calls to avoid duplication of nuclear energy, thus greatly reducing the workload of the designer.
vga_lcd
- VGA/LCD控制 ip核，支持 CRT LCD,支持多种色彩方案。-VGA/LCD control ip core, support CRT LCD, supports a variety of color schemes.
Altera FFT IP核 使用实例
- Verilog，关于如何调用Altera官方的FFT iP核，如何输入和得到输出的实例。
基于DSPBuilder与MC8051软IP核的调幅发生器的FPGA设计
- 基于DSPBuilder与MC8051软IP核的调幅发生器的FPGA设计
xapp1052
- ML605开发版 生成IP核的时候选择250MHZ pcie2.0 X4 5Gb/s 其他参考PDF文档。(When the ML605 development version generates the IP kernel, select 250MHZ pcie2.0 X4 5Gb/s Other reference PDF documents.)
microsemi
- microsemi的Libero IDE 软件内部IP核详解(Microsemi's Libero IDE software internal IP kernel details)
ip核
- 购买的beckoff公司的ip核，提供了详细的datasheet以及协议说明，附上调用ip核的文件，采用verilog编写，平台可以在ISE里自己设置(Buy the beckoff company's ip kernel, provides a detailed datasheet and protocol descr iption, attached to the ip kernel file, using verilog prep
ROM_test
- 使用quartus调用ROM的IP核，并生成激励文件进行仿真(Use the quartus call ROM IP kernel, and generate incentive files for simulation.)
cordic_ds249
- FPGA开发过程中的IP核，用于计算正弦，余弦和正切等。(IP core used in FPGA design to calculate cos and sin.)
FSK
- 首先利用IP核记录sin和con波形，然后进行FSK调制，信息为数字信息(Firstly, the IP kernel is used to record the sin and con waveforms, and then the FSK is modulated, and the information is digital information)
dac_controller
- 以ip核的形式来控制数模转换芯片，减少cup开支。(dac controller ip /dac controller)
simon_IP
- 实现总线加密或解密的IP核（APB总线）（含tb测试平台）(Realization of encryption and decryption of IP core (APB bus))
iir_2n_ip_float_demo
- 使用altera提供的ip核，实现了浮点数运算的2阶iir滤波器，结果与matlab运算结果相同。(Using the IP core provided by Altera, the 2 order IIR filter of floating point operation is implemented, and the result is the same as that of MATLAB operation.)