搜索资源列表
USB_1.1IP核
- 这是USB的一个机遇FPGA的IP核设计。欢迎大家使用
IP core
- VHDL ip core的设计，软核的设计方法-VHDL core of the design, soft-core design
uart_verilog
- 包含UART口的VERILOG源程序，该程序在FPGA上验证通过，可作为芯片设计，或FPGA设计的一个完整IP核，硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can
经典高速乘法器IP
- 乘法器是硬件设计中的很常见也很重要的一个模块，它的VHDL硬件实现很好的解决了软件编程中做乘法速度慢的问题，在实时高速系统应用中或DSP软核或数字信号处理硬件实现算法中，经常能使用到乘法器，所以经典的高速乘法器IP 很有参考价值-Multiplier is a common and important module in hardware designing.Its VHDL addresses the low speed of mul
MC8051 IP Core
- 8051的IP软核，使用硬件描述语言编写，可以下载到FPGA/CPLD中作为片上系统的处理器-8051 IP soft-core, the use of hardware descr iption language can be downloaded to the FPGA/CPLD as a system-on-chip processor
USB IPcore（带说明）
- USB IPcoreIP核，包含文档（带说明）-USB IPcoreIP nuclear contains documents (with the note)
8051IPCORE
- VHDL写成的8051IP核，仔细看能有不少收货-written in VHDL 8051IP nuclear, look very carefully to have a receipt
DES_IP
- 是VDKL语言实现的DES算法，是一个IP核， 对于相关方面有很好的帮助-VDKL language of the DES algorithm is an IP core, related well with the help of
8051_ip_core
- 8051微控制器的ip 核的vhdl源代码,其中包含了相应的测试程序.-8051 micro-controller ip nuclear vhdl source code, which contains the corresponding test procedures.
fftipcore
- 该程序是vhdl语言编写的fft变换的ip核代码，程序中共包含了36个.vhd文件-that the procedure was prepared by the vhdl language fft transform ip nuclear code CPC procedures contained 36. vhd documents
DEMO_62
- 16位CUPIP核,完全运行的好的东西,可以直接拿来用的!-16 CUPIP nuclear, full of good things to run, can be directly used to use!
Audio_DAC_FIFO
- altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以用一条语句实现，音频解码的输出。-altera
DM9000A
- altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以轻易实现对dm9000a网卡的控制。-altera
fft_IPcore
- 这是一个fft的IP核，安装要求为quartus6.0以上。解压安装后可在quartus里例化使用，元件主要为cyclone和stratix,最大支持1024点的转换。
ISP1362
- ISP1362的IP核，可直接用于nios II的应用里，在DE2板子直接使用-ISP1362 s IP core, can be used directly in nios II applications, the direct use in the DE2 board
core_arm.tar
- ARM7系统IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-ARM7 System IP Core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
keyboardcontroller.tar
- 键盘控制电路IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-Keyboard control circuit IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
sdram_ctrl.tar
- SDRAM控制IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-SDRAM control IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
LCD_Controller_Altera_MAX_II_CPLD
- 基于MAXII CPLD的对1602字符型液晶进行读写操作，其中使用了一个CFI的IP核-MAXII CPLD-based character LCD on the 1602 to read and write operation, which uses a CFI of the IP core
SRAMCotroller
- 一个SRAM控制器的IP核，很不错，有兴趣的朋友可以下去-An SRAM controller IP core, very good friends who are interested can go on