搜索资源列表
mc8051_vhdl
- mcs51的vhdl IP核,是每个学习FPGA的必经之路，希望一起探讨-mcs51 the vhdl IP core, each is a must to learn FPGA, hoping to explore together
8-bit-mcu-ip-core-design-and-verification
- 万方数据库中载的，关于IP核设计和验证方面的论文-popular database containing, for the IP core design and certification papers
LCD_IP_code
- LCD的通用驱动电路IP核设计..... -generic LCD driver circuit IP Core Design ...
my_ip_core
- 在quartusII下用verilog语言自己写的IP核，对FPGA开发初学者有帮助的。-in quartusII verilog using their own language to write the IP core, FPGA development beginners to help.
led_pwm
- 用硬件描述语言实现的灯控IP核，可实现至少256种颜色的真彩变换。-using Hardware Descr iption Language lights control IP core can achieve at least 256 colors transform the sleekly.
usb_funct[1].tar
- usb2.0的IP核，可在QuartusII或MaxPlusII环境下实现编译和生成ip核-usb2.0 IP nuclear, QuartusII or the environment under MaxPlusII compile and generate nuclear ip
fft
- VHDL语言编写的fft变换的ip核代码 对算法感兴趣的可以-VHDL language fft transform algorithm ip core code can be interested in
pci_core
- PCI logicore,在某网站上下载的ip核文件，希望具有参考价值，-PCI logicore, at a certain site to download the ip nuclear document, hoping that with a reference value,
VGAControllercomponent
- altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以轻松控制vga的显示，十分难得哦！-altera
userlogicOpenI2C
- altera的ip核， 添加后，在quartusII中可以轻松实现对i2c的控制，是fpga开发人员的必备工具之一。-altera
generic_avalon_sram
- 一个比较有参考价值的sram IP核，对SOPC感兴趣的人士有一定的指导意义！该程序是采用avalon总线，可以直接内嵌进SOPC Builder。-A comparison reference value has sram IP core, on the SOPC interested people have a certain guide! The procedure is used avalon bus, can be direc
or1k[1].tar
- 好东西啊,PCI的IP核.大家快下吧.@可以用来参考.FPGA设计的-Ah good things, PCI
CAN_IPCore
- CAN_IPCore CAN协议的IP核源代码 verilog 语言
cordic_4
- cordic的ip核，在国外的网站上搞到的~-CORDIC
ip_fft128
- 128点fft的IP核vhdl源代码，另有其控制代码。-128 point fft s IP core VHDL source code, while its control code.
fftinterface
- 电赛一等奖作品：音频信号分析仪的FPGA源码，VHDL编写，Quartus7.1综合，ModelSim6.2g se仿真，应用了opencores.org上的开源FFT IP核，加入了8051总线接口和ram-Xinhua Cup first prize works: audio signal analyzer FPGA source, VHDL prepared, Quartus7.1 integrated, ModelSim6.2g
ml505_pcie_x1_plus
- Xilinx 公司PCI Express IP核应用参考设计。通过这个样例，用户可以掌握PCI Express应用设计的一般方法，了解PCI Express的工作原理。-Xilinx Inc. PCI Express IP core reference design applications. Through this example, the user can master the application of the design
SoC_WishboneSystem
- SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
OCPSpecification
- OCPSpecification 2.2，OCP-IP组织提出的IP核互联的规范，详细的使用说明文档。-OCPSpecification 2.2, OCP-IP organization of the IP core interconnection norms, the use of detailed documentation.
systemcaes.tar
- 面积最小的AES高级加密算法实现，和此代码的测试程序，可作为一个IP核直接使用，可减少开发人员的设计时间-The smallest AES Advanced Encryption Algorithm, and test procedures for this code can be used as a direct use of nuclear IP, developers can reduce design time