搜索资源列表
USBipcore
- usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
wishbone_VHDL
- wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快 成为ip通信的主流-Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of
8051
- alter公司的mcu核，8051ip核，为quartus2设计，其他应该兼容 -alter the company' s mcu nuclear, 8051ip nuclear, for quartus2 design should be compatible with other
usb11
- 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。-Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
can
- 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
uart8
- 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。-Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation pr
studyFFTcore
- 调用FPGA的IP核实现FFT运算，在xilinx的vertex4sx55FPGA的实现-Call FPGA implementation of the IP core FFT computation, in the Xilinx implementation of the vertex4sx55FPGA
SQRT_IP
- FPGA开发用，开平方的IP核，可供初学者快速上手。-IP
USB2.0IP
- 完整的用VERILOG语言开发的USB2.0 IP核源代码,包括文档-Complete Verilog language developed by USB2.0 IP core source code, including documentation
CAN_IP
- 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
I2C
- IIC通信协议IP核，描述IIC协议在FPGA上的实现-IIC communications protocol IP core
Character_LCD
- 这是一个 NIOSII系统的 1602LCD 控制IP核-This is a system NIOSII nuclear 1602LCD control IP
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051
slaveController
- 对USB的从机设备的IP核进行了重新设计并在一定程度上进行了优化-On the USB device from the IP core has been redesigned to some extent, is optimized
RTL
- 对usb设备控制的ip核进行了重新设计并进一步优化-Usb device on the control of nuclear ip has been redesigned and further optimize
AteralIP
- Altera IP核8B10B编码器的完整设计流程包括Altera IP的定制、仿真和实现的全过程-Altera IP core of the integrity of the 8B10B encoder design process, including the Altera IP customization, simulation and realization of the whole process of
FPGA
- 利用FPGA的51 IP核实现与单片机和ARM的串口通信-FPGA connect with MCU and ARM
SmartSOPC_Component
- smartSOPC NIOS IP core，周立功FPGA实验箱IP核-smartSOPC NIOS IP core, Zhou Ligong FPGA experimental box IP core
fequency
- 一款可用于数字频率计设计的IP核,使用该IP核科研构建基于SOPC技术的片上数字频率计，测频范围较宽。-A digital frequency meter using IP core
zlg_avalon_lcd128_64
- 基于avalon的12864液晶模块ip核-The 12864-based LCD module avalon nuclear ip