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Wishbone
- wishbone总线协议详细的技术说明文挡！-wishbone bus protocol detailed technical descr iption of the text block!
WISHBONE中文版
- 片上总线协议WISHBONE B4中文版，帮助英文不是很好的同学快速学习这个总线协议
wbspec_b3
- soc中ip核集成时所采用的一种片上总线，开发的，为opencores所采用，wishbone片上总线指南-were integrated ip nuclear adopted by an on-chip bus, development, for opencores using the on-chip bus wishbone Guide
Wishbone
- wishbone总线协议详细的技术说明文挡！-wishbone bus protocol detailed technical descr iption of the text block!
wb_conbus.tar
- wishbone 源代码，opencore-wishbone source code, opencore
wishbone_i2c_master
- -- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Ose
adma
- Wishbone dma ip core
simple_spi
- 一个简单的ＳＰＩ ＩＰ核，SPI Core Specifications 可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral I
rs232_syscon_v
- This a state-machine driven rs232 serial port interface to a "Wishbone" // type of bus.-This a state-driven machine rs232 seria l port interface to a "Wishbone"// type of bus.
wishbone_i2c_master_vhd
- WISHBONE revB2 compiant I2C master core
opencores_i2c_master
- i2c VHDL,能够实现I2C 用的是wishbone总线
Wishbone_from_opencores
- 这个是在ＯＰＥＮＣＯＲＥ上收集的wishbone总线的开发说明和指导，随着电子设计开源ＩＰ的大量应用，wishbone总线也越来越普及。-This is collected in OPENCORE Wishbone bus and guide the development of note, with the electronic design of a large number of open source IP applicatio
OptimizationofaDoubleWishboneSuspensionSystem
- This demo shows how to use MATLAB, Optimization Toolbox, and Genetic Algorithm and Direct Search Toolbox to optimize the design of a double wishbone suspension system.
SoC_WishboneSystem
- SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
opb_wb
- 这是一个连通OPB和Wishbone Bus的Bridge, 能够让OPB与开源的Wishbone Bus连接通信， 从而使用基于Wishbone的许多开源IP Core-This is a Wishbone Bus connectivity OPB and the Bridge, that allows OPB and the Wishbone Bus to connect the open source communications
The_Analyse_And_Research_of_embeded_SoC_Bus
- 本文主要介绍和分析了在集成芯片设计中几种常用的片上系统总线－CoreConnect 总线、MBA 总线、Wishbone 总线和OCP 总线，通过比较这些总线的特性及适用范围，展望了它们的发展前景。-This paper introduces and analyzes the design of integrated chips in several commonly used system-on-chip bus-CoreConnec
wisbone_2_ahb.tar
- ---- ---- ---- WISHBONE Wishbone_BFM IP Core ---- ---- ---- ---- This file is part of the Wishbone_BFM project ---- ---- http://www.opencores.org/cores/Wishbone_BFM/ ---- ---- ---- ---- Descr iption ---- --
wb_rtc
- // -*- Mode: Verilog -*- // Filename : wb_master.v // Descr iption : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Up
wbspec_b3
- Introduce the wishbone bus .
wishbone
- wishbone IP CORE Verilog quartus-wishbone IP CORE Verilog quartusii