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dclocke
- vhdl数字时钟设计 目的,原理仿真 源程序-vhdl digital clock designed, the principle source Simulation
verilog50%
- 本文主要介绍了50%占空比三分频器的三种设计方法,并给出了图形设计、VHDL设计、编译结果和仿真结果。设计中采用EPM7064AETC44-7 CPLD,在QUARTUSⅡ4.2软件平台上进行。 -This paper introduces a 50% duty cycle three dividers of the three design methods, and gives the graphic design, VHDL d
2006110175721
- VHDL数字控制系统设计范例,非常好的一个资料哈-VHDL digital control system design examples, a very good information Kazakhstan.
8b10b_Encoder
- 应用VHDL设计的8b10b 编码器,对串行数据的高速传输有用。-application VHDL design 8b10b encoding device to the high-speed serial data transmission useful.
8b10b_Decoder
- 应用VHDL设计的8b10b解码器源文件,实现高速的串行数据传输。-application VHDL design 8b10b decoder source, the realization of high-speed serial data transmission.
traffic_control
- 设计制作一个用于十字路口的交通灯控制器 有一组绿、黄、红灯用于指挥交通,绿灯、黄灯和红灯的持续时间分别为20秒、5秒和25秒; 当有特殊情况(如消防车、救护车等)时,两个方向均为红灯亮,计时停止,当特殊情况结束后,控制器恢复原状态,继续正常运行-design a crossroads for the traffic signal controller is a group in green, yellow and red li
VHDL3-8
- 用VHDL设计的3-8译码器,精简~!-design using VHDL 3-8 decoder, streamlining ~!
VHDLLED
- 用VHDL设计8*8点阵显示阵字~~~~!-8* 8 character dot-matrix display RUF ~~~~!
banjiaqichengxu
- 用VHDL设计一个4位二进制并行半加器,要求将被加数、加数和加法运算和用动态扫描的方式共阴数码管一同时显示出-VHDL design a four-parallel binary adder, requesting summand, addends and multiplications and dynamic scanning of a total of Yam Digital also showed a
cpldTo8051
- CPLD与8051的总线接口的VHDL设计源码,包括原理图,VHDL语言的源程序,仿真波形,设计的详细说明-CPLD and 8051 bus interface VHDL design source code, including drawings, VHDL source, waveform simulation, design details
VHDL
- 基才VHDL状态机设计的智能交通控制灯 设计 有需要的可以看一下-only VHDL-based state machine design and intelligent traffic control lights need to design can look at the
VHDL
- 基才VHDL状态机设计的智能交通控制灯 有需要的可以看一下-only VHDL-based state machine design and intelligent traffic control lights need to see what
VHDL
- VHD设计实例8位加法器的设计分频电路数字秒表的设计-VHD Design 8 adder design of sub-frequency circuit design of digital stopwatch
vhdlYONGHUSHOUCE
- 非常优秀的国外VHDL设计教程,可进行MODELSIM模拟等操作-Excellent foreign VHDL design tutorial, it can conduct operations such as ModelSim Simulation
VHDL
- vhdl语言设计资料,学习FPGA设计的好书籍。-vhdl脫茂脩脭脡猫 录 脝 脳 脢脕脧 拢 卢 脩 搂 脧 掳 FPGA脡猫 录 脝渭脛 潞 脙脢茅 录 庐 隆 拢
cpu-leon3-altera-ep1c20
- 一个使用VHDL设计的具有强大功能的32位CPU,这个文件包含了在Altera公司的ep1c20 FPGA的位码文件和配置文件,可以直接下载使用!-A VHDL design with the use of powerful 32-bit CPU, this document contains Altera Corporation in the ep1c20 FPGA code and configuration files, you
cpu-leon3-altera-ep2s60-ddr
- 一个使用VHDL设计的具有强大功能的32位CPU,这个文件包含了与之配套的DDR控制器程序!-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!
VHDl
- VHDL数字控制系统设计范例,PDG格式的,希望对大家有用!-VHDL Examples of digital control system design, PDG format, in the hope that useful to everybody!
VHDL
- 本系统使用VHDL语言进行设计,采用自上向下的设计方法。目标器件选用Xilinx公司的FPGA器件,并利用Xilinx ISE 7.1 进行VHDL程序的编译与综合,然后用Modelsim Xilinx Edition 6.1进行功能仿真和时序仿真。-The system design using VHDL language, using top-down design method. Selection of the target d
shuzizhong
- 介绍了用VHDL设计数字钟的相关知识,是学习VHDL的经典例子.-Introduction with VHDL design knowledge digital clock is a classic example of learning VHDL.