搜索资源列表
DPLL1lp
- 频带数字通信中，频带一阶锁相环simulink模型-band digital communications, a frequency band PLL Simulink model
digital_loopback
- 基于ti公司6713dsp的数字锁相环，运行环境为ccs3.1。希望有所帮助。-ti-based company 6713dsp the DPLL, the operating environment for ccs3.1. Want some help.
060107[1].pdf
- 全数字锁相环,包括ＤＰＤ，ＤＬＦ，ＤＣＯ．-DPLL, including the DPD, DLF, the making.
sdui
- 用数值计算方法研究三阶锁相环的非线性性能及其改善途径.建立具有正弦鉴相特性的三阶锁相 环的动态非线性微分方程 ,通过编制数值解程序 ,求出不同条件下的相轨迹和时间响应图 ,分析了电路参数和初 始条件对三阶锁相环非线性性能的影响 ,并提出改善非线性性能的途径.-numerical calculation method PLL third-order nonlinear properties and improved ways. E
s72369
- 508a的控制锁相环的程序，这次不会重了吧 老子自己写的-508a of the PLL control procedures, this will never come to the point I wrote it myself
203.6M
- 508单片机，控制si4133单片锁相环产生203.6mhz的频率-508 microprocessor, control si4133 PLL frequency generated 203.6mhz
all_digital_phase_locked_loop
- 一篇关于数字锁相环的很好的文章，费了很大力气才搞到的-a DPLL on the good paper, and a great effort will involve the
changyongmokuai
- 智能全数字锁相环的设计用VHDL语言在CPLD上实现串行通信-DPLL intelligent design using VHDL on the CPLD Serial Communication
200761311574149479
- 介绍了如何使用数字锁相环,如何用VHDL实现数字锁相环-on how to use the DPLL, how to use VHDL DPLL
MC145159PLL
- 基于MC145159的PLL频率合成器设计与实现 介绍了锁相环路频率合成器的基本原理,分析了集成锁相环芯片M C 145159的工作特性,给出了集成锁相环芯片M C 145159的一个应用实例,为高频频率合成器的设计提供了一个较好的思路.测试结果证明了设计的合理性与实用性,系统频率稳定度优于10-7.-MC145159 PLL frequency synthesizer design and realization of PLL f
PID
- PID算法，实现积分，微分等锁相环的功能，以及相关利用。-PID algorithm, the realization of integral, differential, such as phase-locked loop function, as well as related use.
DPLL
- 介绍了一宽带的数字锁相环的实现方法，欢迎大家踊跃下载 -Introduction of a broadband digital phase-locked loop method, enthusiastically welcomed the U.S. Download
digtal_radio_design
- 数字式调频收音机设计 介绍利用数字锁相频率合成技术构成收音机的电调谐部分并阐述了收音机的调台、选台、搜索与存储等功能的电路设计原理,着重介绍了用收音机集成芯片CXA1019S构成的FM电路、频率合成器芯片BU2614构成的锁相环电路。
PLL
- 几个锁相环仿真程序－通信技术－不记得哪来的啦。希望有用……。-Several phase-locked loop simulation program- communication technologies- do not remember you come from. Seek to help ... ....
code
- 数字锁相环的源代码。用硬件编程语言VHDL编写。-Digital phase-locked loop
ShuZiSuoXiangHuan
- 数字锁相环数学模型,对有研究信号调制的数学建模.-Digital phase-locked loop mathematical model of research has the mathematical modeling of signal modulation.
DigitalPLL
- 一篇简单易懂的关于数字锁相环概念原理设计的经典文章-An easy-to-read digital phase-locked loop on the concept of the classic principles of design article
02
- 基于VHDL的全数字锁相环的设计 有关键部分的源代码 hehe !-VHDL-based all-digital phase-locked loop has a key part of the design of the source code hehe!
new00
- 锁相环在通信中使用非常普遍，此代码用matlab编写，经过测试通过，锁相环仿真（源程序与仿真结果）-Phase-locked loop used in the communication is very common, this code using matlab prepared, tested and approved, phase-locked loop simulation (source code and simulation
wwy_bysj
- 一个程控锁相环PLL程序,可以设定频率,步进-A program-controlled phase-locked loop PLL procedures, you can set the frequency stepping