搜索资源列表
pll
- 收集的数字锁相环设计相关文章多篇.主要采用VHDL语言进行设计.-Collection of digital phase-locked loop design articles related articles. Mainly VHDL design languages.
PLL
- 可以实现自动锁相环功能的C源程序代码模块，-Can be achieved automatically PLL function C source code modules,
Untitled1
- 锁相环一阶环的设计的仿真。自动画出线性和非线性的仿真结果-First-order phase-locked loop design simulation. Automatically draw linear and nonlinear simulation results
fq_div
- pll 的64倍频 锁相环技术用 实现倍频 从而达到对频率的分频-pll 64 multiplier PLL multiplier used to achieve so as to achieve the sub-band of frequencies
111
- 数字鉴相器,数字锁相环频率合成系统FPGA的实现,很有借鉴价值-Digital phase detector, digital PLL frequency synthesizer system FPGA realization of referential value
006
- 基于FPGA实现的一种新型数字锁相环-Based on the FPGA realization of a new digital PLL
timer_trigger_adc_PLL_SUCCESS
- DSP2407定时器触发ADC，并且进行软件锁相环的实现。-DSP2407 timer to trigger ADC, and the realization of a software phase-locked loop.
newDPLLdesign
- 使用VHDL语言进行数字锁相环的设计，pdf格式，可以打开-The use of VHDL language design of digital phase-locked loop, pdf format, you can open
NewWayOfDPLLdesign
- 使用VHDL语言进行设计DPLL（数字锁相环）的相关文件-The use of VHDL language design DPLL (digital phase-locked loop) of the relevant documents
DPLL2
- 全数字锁相环电路的研制，使用的是VHDL语言 -All-digital phase-locked loop circuit development, using the VHDL language
DPLL(VHDL)
- 使用VHDL语言进行的数字锁相环的设计，里面有相关的文件，可以使用MUX+PLUS打开-The use of VHDL language of digital phase-locked loop design, there are relevant documents, you can use MUX+ PLUS Open
FPGA444555443
- 基于FPGA的全数字锁相环设计,内有设计过程和设计思想-FPGA-based all-digital phase-locked loop design, with the design process and design thinking
phase_lock_vhdl
- 在VHDL下实现锁相环的源码和说明文档.通常用于分频或倍频时进行相位锁定.-To achieve phase-locked loop in the VHDL source code and documentation. Normally used when the frequency or frequency-doubling phase locked.
pll
- 关于数字锁相环方面的代码,觉得还可以，或许对大家有用-the code of the pll
11112323
- 基于锁相环Top-down的建模方法在MATLAB环境下建立数字锁相环完整的仿真模型，并用SIMULINK对数字锁相环的仿真模型进行仿真。 -Top-down phase-locked loop based on the modeling method in MATLAB environment DPLL set up a complete simulation model, and use of digital phase-locke
FrequencySynthesisbyPhaseLock
- 书籍频综和锁相环的Matlab源代码，对频综和锁相环的设计很有帮助；-Books PLL Frequency Synthesizer and the Matlab source code for PLL Frequency Synthesizer Design and helpful
pll
- 实现同步时采用锁相环，锁相环实现的原理，及源代码，-Implementation of the principle of phase-locked loop, and the source code,
shuzisuoxiang
- 数字锁相环(DPLL)技术在数字通信、无线电电子学等众多领域得到了极为广泛的应用。与传统的模拟电路实现的PLL相比，DPLL具有精度高、不受温度和电压影响、环路带宽和中心频率编程可调、易于构建高阶锁相环等优点。-Digital phase-locked loop (DPLL) technology in digital communications, radio electronics, and many other fields ha
chenggong1204
- 用单片机控制锁相环，倍频数由外设键盘输入，输了频率范围0.1KHZ到80KHZ-89C51+PLL
suoxianghuan
- 此为锁相环函数发生器 包括键盘扫描程序 频率显示程序 波形显示程序-This is the phase-locked function generators including the keyboard scanner frequency waveform display shows process procedures, etc.