搜索资源列表
easy_pll
- easy pll,很好的PLL(锁相环设计工具)!-easy pll, good PLL (phase-locked loop design tools)!
200710073
- 锁相环的基本组成 锁相环的工作原理 锁相环的应用-Phase-locked loop composed of the basic working principle of phase-locked loop PLL Application
lock
- 锁相环程序，可以用。 主要是c语言风格的，在 matlab下也可以用-PLL procedures can be used. Mainly c-style language in matlab can also be used under
testbench
- 一个自己编写的全数字锁相环及其测试向量，比较简单但功能基本达到。-I have written an all-digital phase-locked loop and its test vectors, relatively simple to achieve but the basic function.
LABVIEW_suoxianghuan
- LABVIEW模拟锁相环的程序。程序一般，可供参考-LABVIEW analog phase-locked loop procedure. Procedures generally available for reference
sch02
- 下了点关于数字锁相环的东东,下了点关于数字锁相环的东东.-A point on the digital phase-locked loop of Dongdong, a point on the digital phase-locked loop of Higashi.
digitalPLL
- 数字锁相环实现源码，有很大的参考价值。 由 鉴相器 模K加减计数器 脉冲加减电路 同步建立侦察电路 模N分频器 构成.-DPLL realize source, has a great reference value. By the phase detector counter modulus K addition and subtraction circuit synchronous pulse addition and sub
matlab
- pll锁相环仿真程序，经过测试，并附上仿真图，值得学习-pll phase locked loop simulation program, tested with the simulation map, it is worth learning
phase_detector_top_v1.1
- 使用virlog语言编写的一个 锁相环的程序。可直接在cpld中应用。-Virlog languages use a phase-locked loop procedure. Can be directly applied in the CPLD.
LMX2326
- 基于单片机控制锁相环的程序设计，采用AT89S52编程控制LMX2326-Single-chip PLL-based control procedures designed to control AT89S52 programming LMX2326
PLL
- 自己写的一个锁相环程序，希望对大家有所帮助-A phase-locked loop to write their own procedures, we hope to be helpful
C8051F12X
- c8051f120实现锁相环程序供你参考-c8051f120 procedures to achieve phase-locked loop for your reference
sendDataPLL
- 锁相环TB31202的c驱动程序，本人刚完成的项目采用的。运行正常！容易移植-TB31202 the c phase-locked loop driver, I have just completed the project adopted. Operating normally! Easy to transplant
dpll
- 数字锁相环，采用costas环的数字形式，实现跟踪载波相位，-Digital phase-locked loop, using the digital form costas loop to achieve carrier phase tracking,
pll
- 仿真了锁相环工作到一定时间后达到锁定状态的过程，程序采用的是一阶RC低通滤波器即二阶一型环-Simulation of the PLL to work until after a certain period of time to achieve lock-state process, the procedure is used first-order RC low-pass filter that is second-order on
PLL
- DP256_HCS12_PLL锁相环驱动程序-DP256_HCS12_PLL PLL Driver
pll
- 该程序实现的锁相环，运行环境为matlab，二阶的环路滤波器-The program realization of phase-locked loop, operating environment for matlab, the second-order loop filter
dpll_demo
- 一个实现简单的数字锁相环Verilog代码，本人借鉴网上现有的代码后经修改在Cyclone II上调通实现，里面有ModelSim仿真成功的波形图-A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successfu
A1
- 基于ADF4106的锁相环程序，4106由单片机C8051F530提供控制字，输出频率3.6GHz，已经在单班上进行过调试。-ADF4106 PLL-based procedures, 4106 to provide control by the single-chip C8051F530 word, the output frequency of 3.6GHz, has been carried out in a single cla
UYYTY
- 一种关于高速时钟提取的文章，讲述了锁相环提取时钟的优缺点。-A high-speed clock extraction on the article, described the advantages and disadvantages of phase-locked loop clock extraction.