搜索资源列表
PLL
- 锁相环控制,用的IC是AT89C2051,用P1口做控制,不知大家有没兴趣-PLL control IC is used AT89C2051, using P1 control I do, I do not know you have no interest
MB1504_driver
- MB1504锁相环芯片的51单片机驱动程序,可以根据需要修改合适的分频值来完成频率合成配置.-MB1504 PLL chip 51 Single-chip driver, need to be amended in accordance with the appropriate value of the sub-band frequency synthesizer to complete the configuration.
MCU020
- 数字锁相环控制产生信号程序详解以及控制字计算方法-DPLL Detailed procedures for the control signal and the control method of calculating the word
PLL
- 国外一篇很好的数字锁相环(PLL)设计文档(解压后PLL.pdf),不可不看呦!-Abroad, a good digital phase-locked loop (PLL) design documents (after extracting PLL.pdf), can not look at Yo!
pll1
- 该程序实现的功能是数字锁相环的设计。源代码可以直接进行仿真试验◎-The program s function is to achieve the design of digital phase-locked loop. Source code can be directly carried out simulation test ◎
DigitalPLL
- 介绍数字锁相环的基本结构,详细分析基于FPGA的数字锁相环的鉴相器、环路滤波器、压控振荡器各部分的实现方法,并给出整个数字锁相环的实现原理图。仿真结果表明,分析合理,设计正确。
pll_base_second
- 一个二阶锁相环的SIMULINK仿真模型
suoxianghuan
- 锁相环的仿真以及含有文本,希望能有帮助。锁相环对通信中还是很重要的-Phase-Locked Loop Simulation as well as containing text, hoping to have help. Phase-locked loop of communication is very important
ACarrierTrackingAlgorithmBasedOnFPLL
- 介绍了一种基于锁频锁相环(FPLL)的载波跟踪算法。频率跟踪模块可以适应较大动态范围的频率变化,基于软件的数控振荡器(NCO)模块可以达到极高的频率跟踪精度。由于有锁频环的频率牵引,锁相环路滤波器可以设计得很窄,具有很好的抑噪性能,满足精确跟踪载波相位的要求。因此,该基于FPLL的载波跟踪算法可以适应信号存在较大的动态范围和噪声干扰的应用环境;同时,其鉴频鉴相算法表达式简单,易于用可编程数字器件实现。-Introduce an appr
DesignAndApplicationOfSoftwarePhaseLockLoop
- 一种适于计算机软件化实现的锁相环数学模型,分析不同参数对锁相环捕获和跟踪性能的影响,得出不同情况下参数设定的基本准则。-A computer software suitable for the realization of the phase-locked loop mathematical model, analysis of different parameters on the phase-locked loop tracking
DEMO1_KEY_LED
- KX_DVP3F型FPGA应用板/开发板(全套)包括: CycloneII系列FPGA EP2C8Q208C8 40万们,含20M-270MHz锁相环2个。 RS232串行接口;VGA视频口 高速SRAM 512KB。可用于语音处理,NiosII运行等。 配置Flash EPCS2, 10万次烧写周期 。 ᠏
gfuzzy
- 基于模糊逻辑控制的数字锁相环,用于通信系统中的载波恢复。Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.-Based on fuzzy logic control of digital phase-locked loop for the communication
dds
- 实现dds功能,利用quartus软件, 子模块包括加法器,锁相环,date-rom 利用原图将各模块综合,利用ps2键盘控制频率及相位。-Dds realize functions, using Quartus software, sub-modules including the adder, phase-locked loop, date-rom image to the module using integrated,
suoxianghuan
- 常用的锁相环技术,此程序是我在设计高频电路中运用的,具体见程序,经调试无问题-Commonly used phase-locked loop technology, this program is in the design I used in high-frequency circuits, see the specific procedures, no problem by debugging
pll
- 用FPGA实现数字锁相环,开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE
myDPll
- 本人写的数字锁相环,有模拟数据,学习锁相环很好的材料。参考书“数字锁相环路原理与应用”编写。-I write the digital phase-locked loop, have simulated data, a good phase-locked loop learning materials. Reference book
codeshift
- GPS的matlab程序,用于对产生的ca码进行移位,用在锁相环跟踪中对ca码调增-GPS-matlab procedures used to produce displacement of ca code, used in phase-locked loop tracking of the code increases ca
FPGA-DPLL
- 基于FPGA实现的一种新型数字锁相环-FPGA-based realization of a new type of digital phase-locked loop
costas_loop
- 使用改进的COSTAS环实现锁相环(PLL),应用于高动态的数字化接收系统-COSTAS Central improved to achieve phase-locked loop (PLL), used in high dynamic digital reception system
MC145152
- 1、数字锁相环的单片机代码。 2、单片机与数字锁相环MC145152的应用系统的设计与实现。-1, the single-chip digital phase-locked loop code. 2, microcontroller and digital PLL MC145152 Application System Design and Implementation.